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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:20:29 03/24/2011 
-- Design Name: 
-- Module Name:    Mult_Immediate - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.Definitions.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mult_Immediate is
    Port ( in1 					: in  data_addr_type;
           in2 					: in  data_addr_type;
           is_alu_immediate 	: in  STD_LOGIC;
           output 				: out  data_addr_type);
end entity Mult_Immediate;

architecture Behavioral of Mult_Immediate is

begin

process(in1, in2, is_alu_immediate) is
	begin
		case is_alu_immediate is
			when '0' =>	output <= in1;
			when others =>	output <= in2;
		end case;
end process;

end architecture Behavioral;

